附录A------基于粒子群算法的PID控制器的FPGA实现源程序.doc

附录 A 基于粒子群算法的 PID 控制器的 FPGA 实现源程序--pso 算法控制模块源程序library ieee;use ieee.std_logic_1164.all;--use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;--use lgQQ_pso.all;entity control isport(ctr_clk_P,ctr_ctr_res_l :in std_logic; ov1_1 :in std_logic; --初始化结束信号ov2_1 :in std_logic; --从初始化后的 32 个个体中选择全局最优结束信号ov3_1 :in std_logic; --局部，全局最优更新结束信号ov4_1 :in std_logic; --个体速度计算并判断阀值结束信号ov5_1 :in std_logic; --个位置计算并判断阀值结束信号st2_1 :out std_logic; --启动从初始化后的 32 个个体中选择全局最优选择模块st3_1 :out std_logic; --启动局部，全局最优更新模块st4_1 :out std_logic; --启动个体速度计算并判断阀值模块st5_1 :out std_logic; --启动个位置计算并判断阀值模块cmux1 :out std_logic;cmux2 :out std_logic;cmux3 :out std_logic;cmux4 :out std_logic;cmux5 :out std_logic;random_clk :out std_logic;wr_1,rd_1 :out std_logic;lz_cnt :out std_logic_vector(4 downto 0);iterance :out std_logic_vector(7 downto 0));end control;architecture behavioral of control istype states is (idle,st1,st2,st3,st4,st5,st6,stop);signal current_state:states;signal flag :std_logic; --mux5signal lzcnt :std_logic_vector(4 downto 0);signal iter :std_logic_vector(7 downto 0);beginprocess(ctr_clk_P,ctr_res_1,current_state) --系统主状态机beginif ctr_res_1= 1 thencurrent_state --系统复位wr_1 0 );lzcnt 0 );current_states --群体初始化wr_1 --从初始化后的 32 个个体中选择全局最优wr_1 --局部，全局最优更新wr_1 --个体速度计算并判断阀值wr_1 --个体位置计算并判断阀值wr_1 --新个体位置，速度，局部最优更新后的数据存储wr_1 --迭代结束cuttent_statecurrent_state 0 );--“0000“;over_1 0 );fxi1 0 );else --接收经过一代更新的新个体数据xi2 0 );fix2 0 );end if;end process;end architecture;--从初始粒子群中选择一个全局最优解模块源程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity gbest isport( clk_P,stat_1 :in std_logic;res_1 :in std_logic;x1x2 :in std_logic_vector(31 downto 0);--(31 downto 0);x_fit :in std_logic_vector(23 downto 0);--(m downto 0);address :out std_logic_vector(4 downto 0);gbest :out std_logic_vector(31 downto 0);--(31 downto 0);gb_fit :out std_logic_vector(23 downto 0);over_1 :out std_logic);end gbest;architecture Behavioral of gbest issignal gfit :std_logic_vector(23 downto 0);signal cnt :std_logic_vector( 4 downto 0);type states is ( idle,st1,stop);signal current_state:states;beginprocess(res_1,clk_p,current_state,start_1,x_fit,gfit)--cntbeginif res_1= 1 thencurrent_state 1 );gfit 1 );gbest 1 );over_1over_1 0 ); if start_1= 1 thencurrent_stateover_1x_fit thengbestover_1over_1 1 );max 1 );elsif clk_P event and clk_P= 1 thencase current_state iswhen idle=over_1over_1= 1 ;if fxi fpbi thenpbioover_1over_1over_1over_1“000000011111111111“thenvoutover_1over_1 0 );r2 0 );elsif clk_P event and clk_P= 1 thenz(15 downto 1)over_1over_1“0111111111111111“thenxoutover_1over_1= 0 ;current_state=idle;end case;end if;end process;end Behavioral;--多路选择器 Mux5 模块源程序library ieee;use ieee.std_logic_1164.all;-use ieee.std_logic_arith.all;-use ieee.std_logic_unsigned.all;-use work.canshu.all;entity mux5 isport( mux_ctr,clk_p : in std_logic;xi : in std_logic_vector(15 downto 0);vi : in std_logic_vector(11 downto 0);xi_o : out std_logic_vector(31 downto 0);vi_o : out std_logic_vector(23 downto 0));end mux5;architecture Behavioral of mux5 isbeginprocess(mux_ctr,xi,vi, clk_p)beginif clk_p event and clk_p= 1 thenif mux_ctr= 0 then --接收刚初始化的数据vi_o(11 downto 0) =vi;xi_o(15 downto 0) =xi;else --接收经过一代更新的新个体数据vi_o(23 downto 0) =vi;xi_o(31 downto 0) =xi;end if;end if;end process;end architecture;